1. Field of the Invention
The present invention relates to a dynamic random access memory (hereinafter, "DRAM") cell, and, more particularly, to the structure of such a DRAM cell having a two-tiered arrangement of electrical elements for achieving a high packing density. Even more particularly, the present invention relates to a two-tiered arrangement of a three transistor DRAM cell having, in accordance with different embodiments of the invention, either two or three driving lines in addition to a ground line.
2. State of the Prior Art
Random access memory (RAM) devices, fabricated utilizing metal-oxide-semiconductor (MOS) technology, are widely used as memories of various types of electronic devices, particularly including computers. RAM devices may be of either of two basic, different types, namely static MOS RAM's and dynamic MOS RAM's. Static MOS memories, relative to dynamic MOS memories, usually have higher operating speeds, but also have higher power dissipation. Conversely, whereas dynamic MOS RAM'S (DRAM's) occupy less area on the substrate and have relatively lower power consumption and thus reduced power dissipation, rendering them more suitable for higher density packing, such devices typically have relatively slower operating speeds and require more elaborate control circuits. In view of the relative advantages afforded thereby, and in spite of their limitations as noted, DRAM's are becoming used as high capacity storage devices on an increasing basis. Heretofore, a great deal of effort has been exerted for achieving ever higher packing densities of DRAM's, including designs directed to reducing the number of transistors required for each DRAM cell.
In fact, DRAM cells employing only a single transistor have been developed and are widely used, such single transistor DRAM cells requiring only two control lines, namely, a bit line and a word line. Such single transistor DRAM cells, however, typically require a very sensitive sense amplifier, because the output signal from the cell is read out as a potential difference of the associated bit line of the cell, as produced thereon by a charge stored in the cell capacitance. Particularly, when the cell is read out, a substantial portion of the electrical charge stored in the cell is consumed, or dissipated, in charging up the parasitic capacity of the bit line, thereby substantially reducing the potential difference to a very small value and correspondingly producing a very faint, or weak, output signal. Moreover, as the packing density level increases, there is a tendency in such DRAM cells for the cell capacity to decrease whereas the parasitic capacity of the associated data bit line remains almost unchanged. This tendency contributes to a further reduction in the potential difference and correspondingly the output signal level on the data bit line, and imposes a corresponding requirement of even greater sensitivity of the associated sense amplifiers and/or ultimately, a limitation on the packing density of the DRAM cells which may be achieved.
Other types of DRAM cells have also been developed which overcome the foregoing disadvantages of single transistor DRAM cells, including particularly a number of varieties of three-transistor DRAM cells, an illustrative such cell being shown in FIG. 1.
More particularly, FIG. 1 is a circuit schematic of a prior art, three-transistor DRAM cell comprising transistors T1, T2 and T3 interconnected through a shared read/write (R/W) data bit line DL, and having as individual or separate lines, a read select line RL and a write select line WL respectively connected to the gates of transistors T1 and T2, the drain of transistor T3 being connected to ground. Information is stored in the cell of FIG. 1 in accordance with the potential level of the gate electrode of the storage transistor T3, in the effective gate capacitor C connected between junction A and ground as illustrated in dotted line. The stored information is output on the date bit line DL by switching both the storage transistor T3 and the read select transistor T1 to a conductive state, thus discharging the data bit line DL to ground potential. Because of its circuit configuration and operation, a three-transistor DRAM cell as in FIG. 1, compared to one-transistor such cells, produces a significantly higher difference in the voltage level of the data bit line DL and correspondingly an output signal of significantly higher voltage level. As a result, a relatively more simple sense-amplifier is sufficient for purposes of detecting the output signal from the cell, permitting a reduction in the required area for the sense-amplifier region and effectively a higher packing density of an array of such DRAM cells. On the other hand, in such three-transistor DRAM cells, not only is the number of transistors necessarily greater than in a one-transistor DRAM cell, but also the number of control lines is likewise greater. When the three transistors and associated control lines of such a DRAM cell are arranged on a common plane, the cell thus occupies a relatively large area and adversely affects the packing density which can be achieved.
Accordingly, two-tiered structures have been developed for fabricating three-transistor DRAM cells, in an effort to achieve a few increased packing densities while nevertheless retaining the operational advantages of three-transistor DRAM cells, relative to one-transistor DRAM cells. There nevertheless remains a need for improved arrangements of such two-tiered structures in the interests of achieving improved packing densities while retaining the desired operational characteristics.